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1 LTC1864/ltc1865 18645f applicatio s u features descriptio u typical applicatio u m power, 16-bit, 250ksps 1- and 2-channel adcs in msop single 5v supply, 250ksps, 16-bit sampling adc supply current vs sampling frequency the ltc ? 1864/ltc1865 are 16-bit a/d converters that are offered in msop and so-8 packages and operate on a single 5v supply. at 250ksps, the supply current is only 850 m a. the supply current drops at lower speeds because the LTC1864/ltc1865 automatically power down between conversions. these 16-bit switched capacitor successive approximation adcs include sample-and-holds. the LTC1864 has a differential analog input with an adjustable reference pin. the ltc1865 offers a software- selectable 2-channel mux and an adjustable reference pin on the msop version. the 3-wire, serial i/o, small msop or so-8 package and extremely high sample rate-to-power ratio make these adcs ideal choices for compact, low power, high speed systems. these adcs can be used in ratiometric applications or with external references. the high impedance analog inputs and the ability to operate with reduced spans down to 1v full scale, allow direct connection to signal sources in many applications, eliminating the need for external gain stages. n 16-bit 250ksps adcs in msop package n single 5v supply n low supply current: 850 m a (typ) n auto shutdown reduces supply current to 2 m a at 1ksps n true differential inputs n 1-channel (LTC1864) or 2-channel (ltc1865) versions n spi/microwire tm compatible serial i/o n 16-bit upgrade to 12-bit ltc1286/ltc1298 n pin compatible with 12-bit ltc1860/ltc1861 , ltc and lt are registered trademarks of linear technology corporation. n high speed data acquisition n portable or compact instrumentation n low power battery-operated instrumentation n isolated and/or remote data acquisition 1 2 3 4 8 7 6 5 v ref in + in gnd v cc sck sdo conv LTC1864 1864 ta01 analog input 0v to 5v 5v 1 m f serial data link to asic, pld, mpu, dsp or shift registers sampling frequency (khz) 0.01 supply current ( a) 1000 100 10 1 0.1 0.01 100 1864 ta02 0.1 1 10 1000 microwire is a trademark of national semiconductor corporation. ( datasheet : )
2 LTC1864/ltc1865 18645f operating temperature range LTC1864c/ltc1865c/ LTC1864ac/ltc1865ac ........................ 0 c to 70 c LTC1864i/ltc1865i/ LTC1864ai/ltc1865ai ..................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c supply voltage (v cc ) ................................................. 7v ground voltage difference agnd, dgnd ltc1865 msop package ........... 0.3v analog input ............... (gnd C 0.3v) to (v cc + 0.3v) digital input ................................ (gnd C 0.3v) to 7v digital output .............. (gnd C 0.3v) to (v cc + 0.3v) power dissipation .............................................. 400mw (notes 1, 2) order part number ms8 part marking ms part marking lths ltht ltc1865cms ltc1865ims ltc1865acms ltc1865aims order part number LTC1864cms8 LTC1864ims8 LTC1864acms8 LTC1864aims8 lthq lthr t jmax = 150 c, q ja = 210 c/w t jmax = 150 c, q ja = 210 c/w 1 2 3 4 v ref in + in? gnd 8 7 6 5 v cc sck sdo conv top view ms8 package 8-lead plastic msop absolute axi u rati gs w ww u package/order i for atio uu w ltvl ltvm order part number s8 part marking s8 part marking 1864 1864i LTC1864cs8 LTC1864is8 LTC1864acs8 LTC1864ais8 order part number t jmax = 150 c, q ja = 175 c/w 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so v ref in + in gnd v cc sck sdo conv 1864a 1864ai ltvn ltvp 1865 1865i ltc1865cs8 ltc1865is8 ltc1865acs8 ltc1865ais8 1865a 1865ai 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so conv ch0 ch1 gnd v cc sck sdo sdi t jmax = 150 c, q ja = 175 c/w 1 2 3 4 5 conv ch0 ch1 agnd dgnd 10 9 8 7 6 v ref v cc sck sdo sdi top view ms package 10-lead plastic msop LTC1864/ltc1865 LTC1864a/ltc1865a parameter conditions min typ max min typ max units resolution l 16 16 bits no missing codes resolution l 14 15 bits inl (note 3) l 8 6 lsb transition noise 1.1 1.1 lsb rms gain error l 20 20 mv the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, v ref = 5v, f sck = f sck(max) as defined in recommended operating conditions, unless otherwise noted. co verter a d ultiplexer characteristics u w u consult ltc marketing for parts specified with wider operating temperature ranges.
3 LTC1864/ltc1865 18645f LTC1864/ltc1865 symbol parameter conditions min typ max units snr signal-to-noise ratio 87 db s/(n + d) signal-to-noise plus distortion ratio 10khz input signal 83 db 100khz input signal 76 db thd total hamonic distortion up to 5th harmonic 10khz input signal 88 db 100khz input signal 77 db full power bandwidth 20 mhz full linear bandwidth s/(n + d) 3 75db 125 khz LTC1864/ltc1865 LTC1864a/ltc1865a parameter conditions min typ max min typ max units offset error LTC1864 so-8 and msop, ltc1865 msop l 2 5 2 5mv ltc1865 so-8 l 3 7 3 7mv input differential voltage range v in = in + C in C l 0v ref 0v ref v absolute input range in + input C 0.05 v cc + 0.05 C 0.05 v cc + 0.05 v in C input C 0.05 v cc /2 C 0.05 v cc /2 v v ref input range LTC1864 so-8 and msop, 1 v cc 1v cc v ltc1865 msop analog input leakage current (note 4) l 1 1 m a c in input capacitance in sample mode 12 12 pf during conversion 5 5 pf the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, v ref = 5v, unless otherwise noted. dy a ic accuracy u w digital a d dc electrical characteristics u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, v ref = 5v, f sck = f sck(max) as defined in recommended operating conditions, unless otherwise noted. co verter a d ultiplexer characteristics u w u t a = 25 c. v cc = 5v, v ref = 5v, f sample = 250khz, unless otherwise noted. LTC1864/ltc1865 symbol parameter condition min typ max units v ih high level input voltage v cc = 5.25v l 2.4 v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C 2.5 m a v oh high level output voltage v cc = 4.75v, i o = 10 m a l 4.5 4.74 v v cc = 4.75v, i o = 360 m a l 2.4 4.72 v v ol low level output voltage v cc = 4.75v, i o = 1.6ma l 0.4 v i oz hi-z output leakage conv = v cc l 3 m a i source output source current v out = 0v C 25 ma i sink output sink current v out = v cc 20 ma i ref reference current (LTC1864 so-8 and conv = v cc l 0.001 3 m a msop, ltc1865 msop) f smpl = f smpl(max) l 0.05 0.1 ma i cc supply current conv = v cc after conversion l 0.001 3 m a f smpl = f smpl(max) l 0.85 1.3 ma p d power dissipation f smpl = f smpl(max) 4.25 mw
4 LTC1864/ltc1865 18645f LTC1864/ltc1865 symbol parameter conditions min typ max units v cc supply voltage 4.75 5.25 v f sck clock frequency l dc 20 mhz t cyc total cycle time 16 ? sck + t conv m s t smpl analog input sampling time LTC1864 16 sck ltc1865 14 sck t suconv setup time conv before first sck - 30 ns (see figure 1) t hdi hold time sdi after sck - ltc1865 15 ns t sudi setup time sdi stable before sck - ltc1865 15 ns t whclk sck high time f sck = f sck(max) 40% 1/f sck t wlclk sck low time f sck = f sck(max) 40% 1/f sck t whconv conv high time between data t conv m s transfer cycles t wlconv conv low time during data transfer 16 sck t hconv hold time conv low after last sck - 13 ns note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 4: channel leakage current is measured while the part is in sample mode. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. LTC1864/ltc1865 symbol parameter conditions min typ max units t conv conversion time (see figure 1) l 2.75 3.2 m s f smpl(max) maximum sampling frequency l 250 khz t ddo delay time, sck to sdo data valid c load = 20pf 15 20 ns l 25 ns t dis delay time, conv - to sdo hi-z l 30 60 ns t en delay time, conv to sdo enabled c load = 20pf l 30 60 ns t hdo time output data remains c load = 20pf l 510 ns valid after sck t r sdo rise time c load = 20pf 8 ns t f sdo fall time c load = 20pf 4 ns the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, v ref = 5v, f sck = f sck(max) as defined in recommended operating conditions, unless otherwise noted. reco e ded operati g co ditio s u u u uw w ti i g characteristics u w
5 LTC1864/ltc1865 18645f typical perfor a ce characteristics uw sampling frequency (khz) 0.01 supply current ( a) 1000 100 10 1 0.1 0.01 100 1864/65 g01 0.1 1.0 10 1000 v cc = 5v t a = 25 c conv low = 800ns temperature ( c) ?0 supply current ( a) 1000 800 600 400 200 0 0 50 75 1864/65 g02 ?5 25 100 125 v cc = 5v v ref = 5v f sample = 250khz conv high = 3.2 s temperature ( c) ?0 sleep current (na) 1000 900 800 700 600 500 400 300 200 100 0 0 50 75 1864/65 g03 ?5 25 100 125 conv = v cc = 5v sample rate (khz) 0 reference current ( a) 60 50 40 30 20 10 0 50 100 150 200 1864/65 g04 250 v cc = 5v t a = 25 c v ref = 5v conv low = 800ns temperature ( c) ?0 reference current ( a) 55 54 53 52 51 50 49 48 47 46 45 0 50 75 1864/65 g05 ?5 25 100 125 v cc = 5v v ref = 5v f s = 250khz v ref (v) 0 reference current ( a) 60 50 40 30 20 10 0 1234 1864/65 g06 5 v cc = 5v t a = 25 c f s = 250khz temperature ( c) ?0 analog input leakage (na) 100 1864/65 g09 050 100 75 50 25 0 25 25 75 125 v cc = 5v v ref = 5v conv = 0v code 0 inl error (lsbs) 65536 1864/65 g07 32768 4 2 0 ? ? 16384 49152 v cc = 5v t a = 25 c v ref = 5v code 0 65536 1864/65 g08 32768 16384 49152 dnl error (lsbs) 2 1 0 ? ? v cc = 5v t a = 25 c v ref = 5v supply current vs sampling frequency supply current vs temperature sleep current vs temperature reference current vs sampling rate reference current vs temperature reference current vs reference voltage typical inl curve typical dnl curve analog input leakage current vs temperature
6 LTC1864/ltc1865 18645f typical perfor a ce characteristics uw sinad vs frequency thd vs frequency sfdr vs frequency reference voltage (v) 0 change in offset error (lsb) 75 50 25 0 ?5 4 1864/65 g10 1 2 3 5 v cc = 5v t a = 25 c temperature ( c) ?0 change in offset (lsb) 5 4 3 2 1 0 ? ? ? ? ? 0 50 75 1864/65 g11 ?5 25 100 125 v cc = 5v v ref = 5v reference voltage(v) 0 change in gain error (lsb) 20 15 10 5 0 ? ?0 ?5 ?0 2 4 5 1864/65 g12 1 3 v cc = 5v t a = 25 c temperature ( c) ?0 change in gain error (lsb) 5 4 3 2 1 0 ? ? ? ? ? 0 50 75 1864/65 g13 ?5 25 100 125 v cc = 5v v ref = 5v frequency 1800 1600 1400 1200 1000 800 600 400 200 0 code 1864/65 g14 4 ? ? ? 0 1 23 45 00 1200 1534 127 516 1178 729 v cc = 5v t a = 25 c v ref = 5v frequency (khz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 1864/65 g15 0 20 40 60 80 100 120 f s = 203.125khz f in = 99.72763khz v cc = 5v v ref = 5v t a = 25 c change in offset error vs reference voltage change in offset vs temperature change in gain error vs reference voltage change in gain error vs temperature histogram of 4096 conversions of a dc input voltage 4096 point fft nonaveraged f in (khz) 1 sinad (db) 100 90 80 70 60 50 40 30 20 10 0 10 100 1000 1864/5 g16 v cc = 5v v ref = 5v t a = 25 c v in = 0db snr sinad f in (khz) 1 thd (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 10 100 1000 1864/5 g17 v cc = 5v v ref = 5v t a = 25 c v in = 0db f in (khz) 1 sfdr (db) 100 90 80 70 60 50 40 30 20 10 0 10 100 1000 1864/5 g18 v cc = 5v v ref = 5v t a = 25 c v in = 0db
7 LTC1864/ltc1865 18645f v ref (pin 1): reference input. the reference input defines the span of the a/d converter and must be kept free of noise with respect to gnd. in + , in C (pins 2, 3): analog inputs. these inputs must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. conv (pin 5): convert input. a logic high on this input starts the a/d conversion process. if the conv input is left high after the a/d conversion is finished, the part powers down. a logic low on this input enables the sdo pin, allowing the data to be shifted out. sdo (pin 6): digital data output. the a/d conversion result is shifted out of this pin. sck (pin 7): shift clock input. this clock synchronizes the serial data transfer. v cc (pin 8): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. uu u pi fu ctio s ltc1865 (msop package) conv (pin 1): convert input. a logic high on this input starts the a/d conversion process. if the conv input is left high after the a/d conversion is finished, the part powers down. a logic low on this input enables the sdo pin, allowing the data to be shifted out. ch0, ch1 (pins 2, 3): analog inputs. these inputs must be free of noise with respect to agnd. agnd (pin 4): analog ground. agnd should be tied directly to an analog ground plane. dgnd (pin 5): digital ground. dgnd should be tied directly to an analog ground plane. sdi (pin 6): digital data input. the a/d configuration word is shifted into this input. conv (pin 1): convert input. a logic high on this input starts the a/d conversion process. if the conv input is left high after the a/d conversion is finished, the part powers down. a logic low on this input enables the sdo pin, allowing the data to be shifted out. ch0, ch1 (pins 2, 3): analog inputs. these inputs must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. ltc1865 (so-8 package) sdo (pin 7): digital data output. the a/d conversion result is shifted out of this output. sck (pin 8): shift clock input. this clock synchronizes the serial data transfer. v cc (pin 9): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. v ref (pin 10): reference input. the reference input de- fines the span of the a/d converter and must be kept free of noise with respect to agnd. sdi (pin 5): digital data input. the a/d configuration word is shifted into this input. sdo (pin 6): digital data output. the a/d conversion result is shifted out of this output. sck (pin 7): shift clock input. this clock synchronizes the serial data transfer. v cc (pin 8): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. v ref is tied internally to this pin. LTC1864
8 LTC1864/ltc1865 18645f load circuit for t ddo , t r , t f , t dis and t en voltage waveforms for sdo rise and fall times, t r , t f voltage waveforms for sdo delay times, t ddo and t hdo voltage waveforms for t en sdo 3k 20pf test point v cc t dis waveform 2, t en t dis waveform 1 1864 tc01 sck sdo v il t ddo t hdo v oh v ol 1864 tc02 1864 tc03 conv sdo t en sdo t r t f 1864 tc04 v oh v ol test circuits voltage waveforms for t dis sdo waveform 1 (see note 1) v ih t dis 90% 10% sdo waveform 2 (see note 2) conv note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control 1864 tc05 fu n ctio n al block diagra uu w 1864/65 bd 16-bit sampling adc bias and shutdown convert clk serial port 16 bits in + (ch0) in (ch1) v cc v ref sdo gnd conv (sdi) sck pin names in parentheses refer to ltc1865 data out data in +
9 LTC1864/ltc1865 18645f LTC1864 operation operating sequence the LTC1864 conversion cycle begins with the rising edge of conv. after a period equal to t conv , the conversion is finished. if conv is left high after this time, the LTC1864 goes into sleep mode drawing only leakage current. on the falling edge of conv, the LTC1864 goes into sample mode and sdo is enabled. sck synchronizes the data transfer with each bit being transmitted from sdo on the falling sck edge. the receiving system should capture the data from sdo on the rising edge of sck. after completing the data transfer, if further sck clocks are applied with conv low, sdo will output zeros indefinitely. see figure 1. analog inputs the LTC1864 has a unipolar differential analog input. the converter will measure the voltage between the in + and in C inputs. a zero code will occur when in + minus in C equals zero. full scale occurs when in + minus in C equals v ref minus 1lsb. see figure 2. both the in + and in C inputs are sampled at the same time, so common mode noise on the inputs is rejected by the adc. if in C is grounded and v ref is tied to v cc , a rail-to-rail input span will result on in + as shown in figure 3. reference input the voltage on the reference input of the LTC1864 defines the full-scale range of the a/d converter. the LTC1864 can operate with reference voltages from v cc to 1v. conv t conv sck sdo 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b15 b14 b12 b10 b8 b6 b4 b2 b0* hi-z 1854 f01 hi-z b13 b11 b9 b7 b5 b3 b1 sleep mode t smpl *after completing the data transfer, if further sck clocks are applied with conv low, the adc will output zeros indefinitely 1 2 3 4 8 7 6 5 v ref in + in gnd v cc sck sdo conv LTC1864 1864 f03 v in = 0v to v cc v cc 1 m f serial data link to asic, pld, mpu, dsp or shift registers figure 1. LTC1864 operating sequence figure 3. LTC1864 with rail-to-rail input span figure 2. LTC1864 transfer curve 0v 1lsb v ref ?2lsb v ref ?1lsb v ref v in * *v in = in + ?in 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1864 f02 applicatio s i for atio wu uu
10 LTC1864/ltc1865 18645f ltc1865 operation operating sequence the ltc1865 conversion cycle begins with the rising edge of conv. after a period equal to t conv , the conversion is finished. if conv is left high after this time, the ltc1865 goes into sleep mode drawing only leakage current. the ltc1865s 2-bit data word is clocked into the sdi input on the rising edge of sck after conv goes low. additional inputs on the sdi pin are then ignored until the next conv cycle. the shift clock (sck) synchronizes the data transfer with each bit being transmitted on the falling sck edge and captured on the rising sck edge in both transmitting and receiving systems. the data is transmitted and received simultaneously (full duplex). after completing the data transfer, if further sck clocks are applied with conv low, sdo will output zeros indefinitely. see figure 4. analog inputs the two bits of the input word (sdi) assign the mux configuration for the next requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of the following table. in conv sdi sck 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 sdo b15 b14 b12 b10 b8 b6 b4 b2 b0* hi-z b13 b11 b9 b7 b5 b3 b1 s/d o/s don? care don? care t conv 1864 f04 sleep mode *after completing the data transfer, if further sck clocks are applied with conv low, the adc will output zeros indefinitely hi-z t smpl figure 4. ltc1865 operating sequence applicatio s i for atio wu uu mux address table 1. multiplexer channel selection sgl/diff 1 1 0 0 odd/sign 0 1 0 1 channel # 0 + + 1 + + gnd 1864 tbl1 single-ended mux mode differential mux mode single-ended mode, all input channels are measured with respect to gnd. a zero code will occur when the + input minus the C input equals zero. full scale occurs when the + input minus the C input equals v ref minus 1lsb. see figure 5. both the + and C inputs are sampled at the same time so common mode noise is rejected. the input span in the so-8 package is fixed at v ref = v cc . if the C input in differential mode is grounded, a rail-to-rail input span will result on the + input. reference input the reference input of the ltc1865 so-8 package is internally tied to v cc . the span of the a/d converter is therefore equal to v cc . the voltage on the reference input of the ltc1865 msop package defines the span of the a/d converter. the ltc1865 msop package can operate with reference voltages from 1v to v cc .
11 LTC1864/ltc1865 18645f general analog considerations grounding the LTC1864/ltc1865 should be used with an analog ground plane and single point grounding techniques. do not use wire wrapping techniques to breadboard and evaluate the device. to achieve the optimum performance, use a printed circuit board. the ground pins (agnd and dgnd for the ltc1865 msop package and gnd for the LTC1864 and ltc1865 so-8 package) should be tied directly to the analog ground plane with minimum lead length. bypassing for good performance, the v cc and v ref pins must be free of noise and ripple. any changes in the v cc /v ref voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. bypass the v cc and v ref pins directly to the analog ground plane with a minimum of 1 m f tantalum. keep the bypass capacitor leads as short as possible. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the LTC1864/ ltc1865 have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem if source resistances are less than 200 w or high speed op amps are used (e.g., the lt ? 1211, lt1469, lt1807, lt1810, lt1630, lt1226 or lt1215). but if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conver- sion begins. applicatio s i for atio wu uu 0v 1lsb v cc ?2lsb v cc ?1lsb v cc v in * *v in = (selected ??channel) (selected ?channel) refer to table 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1864 f05 figure 5. ltc1865 transfer curve
12 LTC1864/ltc1865 18645f applicatio s i for atio wu uu u12b 74ac109 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 jp8 246 135 jp9 246 135 2 3 4 1 5 6 7 8 10 9 8 5v dig 5v dig 5v dig 5v dig 5v dig 15v ?5v 5v dig 5v dig 5v an 5v dig 5v dig 5v dig c16 0.1 f c23 0.1 f c5 0.1 f c6 0.1 f c24 0.1 f c18 0.1 f c17 0.1 f 5v dig 5v dig 5v dig c13 0.1 f c26 10 f 6.3v 1206 c14 0.1 f u12a 74ac109 u10 ltc1799 reset clk p0 p1 p2 p3 enp gnd v cc rco q0 q1 q2 q3 ent lo u6 74hc163ad j k clk clr pre q q gnd v cc 1 2 3 5 4 v + gnd set div 14 13 12 15 11 j k clk clr pre q q gnd v cc 16 16 u9b 74ac00 u9a 74ac00 u13b 74ac32 reset clk p0 p1 p2 p3 enp gnd v cc rco q0 q1 q2 q3 ent lo u7 74hc163ad r10 20k 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 j4 3201s40g1 qb qc qd qe qf qg qh gnd v cc qa a oenb lclk sclk reset sqh rn1 330 qb qc qd qe qf qg qh gnd v cc qa a oenb lclk sclk reset sqh r7 51 0pt r9 51 r8 51 0pt c9 180pf c10 680pf opt c8 1000pf opt c12 1000pf opt c7 390pf c11 390pf c27 0.1 f c1 0.1 f c4 0.1 f c21 47pf c22 47pf c25 0.1 f 5v dig c15 0.1 f 5v dig c19 0.1 f c2 1 f 10v 0805 c3 10 f 6.3v 1206 jp3 jp2 jp1 r1 510 r3 2 r2 510 v in v out gnd u1 lt1021-5 v in v out gnd r4 2 15v 15v in + in + agnd in in v ref in + in gnd v cc sck sdo conv u8a 74ac14 u8b 74ac14 u8e 74ac14 u8d 74ac14 u8f 74ac14 out 15v 5v an u4 74hc595adt u5 74hc595adt u9c 74ac00 u9d 74ac00 u13a 74ac32 u13d 74ac32 u13c 74ac32 analog ground plane clk jp6 jp7 jp4 j1 j2 e1 e8 e9 u2 opt u3 LTC1864cms8 1 2 3 4 8 7 6 5 r6 402 1% r5 402 , 1% 1 2 3 4 8 7 6 5 2 2 1 2 1 2 1 2 1 2 1 3 3 2 1 21 4 6 1 2 3 jp5 conv dgnd dgnd dout clkout clkin enable data u8c 74ac14 e2 e3 e7 e6 e4 e5 j3 notes: unless otherwise specified install shunts on jp1, jp3-jp7 pin 1 and pin2; on jp8 and jp9 pin 2 and pin 4, pin 3 and pin 5. 1864/65 ai1 r12 10k LTC1864 evaluation circuit schematic
13 LTC1864/ltc1865 18645f applicatio s i for atio wu uu component side silk screen for LTC1864 evaluation circuit component side showing traces (note wider traces on analog side) bottom side showing traces (note almost no analog traces on board bottom) ground layer with separate analog and digital grounds supply layer with 5v digital supply and analog ground repeated
14 LTC1864/ltc1865 18645f u12b 74ac109 u11 lt1121cst-5 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 2 3 4 1 5 6 7 8 10 9 8 5v dig 5v dig 5v dig 5v dig 5v dig 5v an 5v dig 5v dig c16 0.1 f c23 0.1 f c24 0.1 f c18 0.1 f c17 0.1 f 5v dig c26 10 f 6.3v 1206 u12a 74ac109 u10 ltc1799 reset clk p0 p1 p2 p3 enp gnd v cc rco q0 q1 q2 q3 ent lo u6 74hc163ad j k clk clr pre q q gnd v cc 1 2 3 5 4 v + gnd set div 14 13 12 15 11 j k clk clr pre q q gnd v cc 16 16 u9b 74ac00 u9a 74ac00 u13b 74ac32 reset clk p0 p1 p2 p3 enp gnd v cc rco q0 q1 q2 q3 ent lo u7 74hc163ad 100k rn1 330 c4 0.1 f c3 10 f 6.3v 1206 v in v out gnd r4 2 v ref in + in gnd v cc sck sdo conv out 15v 15v 5v an u13c 74ac32 analog ground plane clk u3 LTC1864cms8 1 2 3 4 8 7 6 5 1 2 3 4 pre d clk clr 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 1864/65 ai2 ro re de di v cc b a gnd 1v to 5v reference 0v to v ref input q v v v q pre d clk clr q v q 5v dig 5v dig 5v dig 5v dig 5v 1 5 2 3 4 500 mc74vhc1g66 120 4 conductor telephone wires to receiver ltc1485 74ac74 74ac74 74ac86 applicatio s i for atio wu uu figure 6. LTC1864 manchester transmitter
15 LTC1864/ltc1865 18645f applicatio s i for atio wu uu 1 2 3 4 8 7 6 5 4 2 3 1 10 12 11 13 5 6 4 2 3 1 5 6 4 2 3 1 5 6 9 8 10 12 11 13 9 8 1864/65 ai3 ro re de di v cc b a gnd pre d clk clr q v q 4 conductor telephone wires to transmitter u1 ltc1485 pre d clk clr q v q ic1a 74ac74 v cc pre d clk clr q v q ic1b 74ac74 ic3b 74ac74 v cc v cc v cc v cc v cc v cc v cc clk clk data data pre d clk clr q v q ic2a 74ac74 clk pre d clk clr q v q ic2b 74ac74 ic4b 74ac08 clk pre d clk clr q v q ic3a 74ac74 clk data in 15v supply to transmitter receive clock at 8 x transmit clock frequency ser sck scl rck 8 15 1 2 3 4 5 6 7 9 qa qb qc qd qe qf qg qh qh in d15 d14 d13 d12 d11 d10 d9 d8 14 11 10 12 13 strobe strobe v ic8 74ac595 v cc ser sck scl rck 8 15 1 2 3 4 5 6 7 9 qa qb qc qd qe qf qg qh qh in d7 d6 d5 d4 d3 d2 d1 d0 14 11 10 12 13 v ic9 74ac595 10 12 11 13 9 8 clk pre j clk k clr q v q ic7b 74ac109 11 14 12 13 15 10 9 data optional serial to parallel converter r1 120 ic5c 74ac86 ic4d 74ac08 ic4c 74ac08 ic6d 74ac32 ic6c 74ls32d ic4a 74ac08 figure 7. LTC1864 manchester receiver
16 LTC1864/ltc1865 18645f applicatio s i for atio wu uu transmit LTC1864 data over modular telephone wire using simple transmitter/receiver figure 6 shows a simple manchester encoder and differ- ential transmitter suitable for use with the LTC1864. this circuit allows transmission of data over inexpensive tele- phone wire. this is useful for measuring a remote sensor, particularly when the cost of preserving the analog signal over a long distance is high. manchester encoding is a clock signal that is modulated by exclusive oring with the data signal. the resulting signal contains both clock and data information and has an average duty cycle of 50%, that also allows transformer coupling. in practice, generating a manchester encoded signal with an xor gate will often produce glitches due to the skew between data and clock transitions. the d flip- flops in this encoder retime the clock and data such that the respective edges are closely aligned, effectively sup- pressing glitches. the retimed data and clock are then xored to produce the manchester encoded data, which is interfaced to telephone wire with an ltc1485 rs485 transceiver. in order to synchronize to incoming data, the receiver needs a sequence to indicate the start of a data word. the transmitter schematic shows logic that will produce 31 zeros, a start bit, followed by the 16 data bits (one sample every 48 clock cycles) at a clock frequency of 1mhz set by the ltc1799 oscillator. sending at least 18 zeros before each start bit ensures that if synchronization is lost, the receiver can resynchronize to a start bit under all condi- tions. the serial to parallel converter shown in figure 7 requires 18 zeros to avoid triggering on data bits. the manchester receiver shown in figure 7 was adopted from xilinx application note 17-30 and would typically be implemented in an fpga. the decoder clock frequency is nominally 8 times the transmit clock frequency and is very tolerant of frequency errors. the outputs of the decoder are data and a strobe that indicates a valid data bit. the data can be deserialized using shift registers as shown. the start bit resets the j-k/flip-flop on its way into the first shift register. when it appears at the qh in output of the second shift register, it sets the flip-flop that loads the parallel data into the output register. with ac family cmos logic at 5v the receiver clock frequency is limited to 20mhz; the corresponding trans- mitter clock frequency is 2.5mhz. if the receiver is imple- mented in an fpga that can be clocked at 160mhz, the LTC1864 can be clocked at its rated clock frequency of 20mhz.
17 LTC1864/ltc1865 18645f ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) msop (ms8) 1001 0.53 0.015 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.077) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) 0.13 0.05 (.005 .002) 0.86 (.034) ref 0.65 (.0256) bcs 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.88 0.1 (.192 .004) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 0.52 (.206) ref 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.04 (.0165 .0015) typ 0.65 (.0256) bsc u package descriptio
18 LTC1864/ltc1865 18645f ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) u package descriptio msop (ms) 1001 0.53 0.01 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) 0.13 0.05 (.005 .002) 0.86 (.034) ref 0.50 (.0197) typ 12 3 45 4.88 0.10 (.192 .004) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc
19 LTC1864/ltc1865 18645f u package descriptio s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 LTC1864/ltc1865 18645f lt/tp 0502 2k ? printed in usa related parts ? linear technology corporation 2001 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com part number sample rate power dissipation description 14-bit serial i/o adcs ltc1417 400ksps 20mw 16-pin ssop, unipolar or bipolar, reference, 5v or 5v ltc1418 200ksps 15mw serial/parallel i/o, internal reference, 5v or 5v 16-bit serial i/o adcs ltc1609 200ksps 65mw configurable bipolar or unipolar input ranges, 5v references lt1460 micropower precision series reference bandgap, 130 m a supply current, 10ppm/ c, available in sot-23 lt1790 micropower low dropout reference 60 m a supply current, 10ppm/ c, sot-23 op amps lt1468/lt1469 single/dual 90mhz, 16-bit accurate op amps 22v/ m s slew rate, 75 m v/125 m v offset lt1806/lt1807 single/dual 325mhz low noise op amps 140v/ m s slew rate, 3.5nv/ ? hz noise, C 80dbc distortion lt1809/lt1810 single/dual 180mhz low distortion op amps 350v/ m s slew rate, C 90dbc distortion at 5mhz u typical applicatio + + 0.1 f 0.1 f 0.1 f 0.1 f 1 f 1 f 0.1 f1 f 100 100 28.7k 10k 4.096v ref 5v 5v 5k 5k 10k 20k 100pf 100pf 5pf 1/2 lt1492 1/2 lt1492 f 1 (0v to 0.66v) f 2 (0v to 2v) 8 4 2 81 7 6 5 4 3 4.096v ref LTC1864 in + in v cc gnd conv sdo sck ref 1860 ta03 sample two channels simultaneously with a single input adc 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 5 10 15 20 25 30 35 40 45 50 frequency (khz) amplitude (db) 1864/65 ta03b f 1 = 7.507324khz at 530mv p-p f 2 = 45.007324khz at 1.7v p-p f s = 100khz 4096 point fft of output

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